1. Field of the Invention
The present invention relates to a semiconductor device controlled by an insulated gate, such as an insulated-gate bipolar transistor, which incorporates an overload protecting or latchup preventing function.
2. Discussion of the Related Art
Referring to FIG. 7, a general description will be given of a known insulated-gate bipolar transistor. The right half portion of FIG. 7 refers to the main body of circuit 10 of an insulated-gate bipolar transistor. An n-type epitaxial layer 113 grown to a predetermined thickness on a solid p-type substrate 111 via a solid n-type buffer layer 112 is used for a wafer or a chip. In addition, the surface of the epitaxial layer 113 is covered with a gate oxide film 114 and further provided with a gate film 115 made of polycrystalline silicon. The gate film 115 is patterned with a number of windows.
P-type base layers 11 and solid n-type emitter layers 12 for the main body 10 are diffused through the windows bored in the gate film 115. An emitter terminal 101 is led from an electrode film 116 for short-circuiting both semiconductor layers on the surface; a gate terminal 102 is led from a gate film 115; and a collector terminal 103 is led from an electrode film 166 beneath the substrate 111. As is obvious from FIG. 7, this insulated-gate bipolar transistor is a vertical type semiconductor device.
When a positive gate voltage is applied to the gate terminal 102 of the insulated-gate bipolar transistor thus constructed in this example, an n-channel is formed on the surface of the p-type base layer 11 beneath the gate film 115. Consequently, electrons are injected from the n-type emitter layers 12 via the formed n-channels to the n-type epitaxial layer 113. The conductivity modulation, based on the electrons thus injected, has the base current supplied to the vertical type pnp transistor including the p-type substrate 111, the n-type buffer layer 112, the epitaxial layer 113, and a p-type base layer 21. When the pnp transistor is turned on, current is caused to flow between the collector terminal 103 and the emitter terminal 101. Consequently, the insulated-gate bipolar transistor is held on.
The insulated-gate bipolar transistor is equivalent to a combination of a field effect transistor and a bipolar transistor and can be represented by the equivalent circuit shown in FIG. 8. Since the insulated-gate bipolar transistor has a four-layer thyristor construction of pnpn including the p-type substrate 111, the n-type buffer layer 112, the epitaxial layer 113, the p-type base layer 21, and an n-type emitter layer 22, a condition called latchup, which makes the control of the insulated gate ineffective, can arise if the thyristor conducts when overload or load-short-circuit occurs. A large current may then thermally break the transistor in a short time.
Latchup ensues from an overload or the like as described above and tends to arise if it is attempted to lower the loss internally caused to increase the performance of the insulated-gate bipolar transistor. In other words, though the amount of electrons to be injected into the epitaxial layer 113 may be increased by shortening the length of the channel beneath the gate film 116 to the advantage of reducing the loss incurred, the voltage drop produced in emitter short-circuit resistance in a portion which short-circuits the emitter layer 22 and the base layer 21 accelerates as the current flowing through the channel increases. Consequently, an npn-type parasitic transistor consisting of the n-type emitter layer 12, the p-type base layer 11, and the n-type epitaxial layer 113 conducts from the injection of the base current from the voltage drop. Thus, latchup is likely to occur.
In this way, breakdown due to latchup must be prevented in order to increase the performance of the insulated-gate controlled semiconductor device by reducing the loss internally caused and the on-state voltage. The present inventor has proposed means for solving the foregoing problems in Japanese Patent application Unexamined Publication No. Hei. 3-97269. Referring to an equivalent circuit diagram of FIG. 8, the general description of the proposal will be given.
As shown in FIG. 8, there is provided a small-sized overload detector 20 or a current detecting cell similar in construction to the main body 10 of the insulated-gate controlled semiconductor device. The overload detector 20 may be fabricated by diffusing the p-type base layer 21 and the n-type emitter layer 22 through the windows of the gate film 115 for the main body 10 in the same manner as described with reference to FIG. 7. The gate terminal 102 and the collector terminal 103 may be used in common with the main body 10. A gate voltage 104 is applied via a gate resistor 30 to a common insulated gate 105 as shown in FIG. 8. Moreover, a current detecting means 40, such as a resistor, is connected to the emitter side of the overload detector 20 as shown in FIG. 8. A field effect transistor 50 whose gate is subjected to the voltage drop of the current detecting means is connected via a resistor 65, for example, to the insulated gate 105 for use in common with the main body 10 and the overload detector 20.
As shown in FIG. 7, the field effect transistor 50 is fabricated by diffusing a p-type well 51, a p-type well connecting layer 52, an n-type source layer 54, and an n-type drain layer 55 through the windows of the gate film 115 isolated from the main body 10.
When the insulated-gate controlled semiconductor device, as shown in the equivalent circuit of FIG. 8, enters the overload state as the load connected to the collector terminal 103 or the emitter terminal 101 short-circuits, for example, the current flowing into the overload detector 20 increases. Thus, the voltage drop of the current detecting means 40 increases. Since the gate of the field effect transistor 50 is subjected to the voltage drop, the transistor becomes operative when the voltage drop value reaches the threshold value of the gate and lowers the voltage applied to the insulated gate 105 by dividing the gate voltage 104 through the on-resistance, the resistor 65, and the gate resistor 30 to prevent latchup by restricting or cutting off the current flowing into the main body 10. In this case, the resistor 65 is used to set a dividing ratio of the gate voltage 104 to lower the voltage applied to the insulated gate 105, but it may be omitted as occasion demands.
Although latchup can be prevented theoretically in the insulated-gate controlled semiconductor device having the equivalent circuit of FIG. 8, the withstand voltage of the field effect transistor 50 actually tends to be deficient. Consequently, while the insulated-gate controlled semiconductor device is held off, latchup may develop in the field effect transistor 50. Moreover, the overload protective operation of the field effect transistor 50 may concur to produce unnecessary oscillation when the load of the insulated-gate controlled semiconductor device shows a short-circuit.
The reason for the first problem lies in the fact that because the p-type well 51 of the field effect transistor 50 of FIG. 7 together with the respective p-type base layers 11 and 21 are diffused during the manufacturing process, the impurity concentration remains too high for the field effect transistor. In other words, the impurity concentration in the main body 10 has to be set to at least about 10.sup.17 atoms/cm.sup.3 to reduce the emitter short resistance as much as possible with the emitter layer 12 in view of latchup prevention. The above-specified impurity concentration is also used to set the operating threshold value of the insulated gate to within the range of 3 to 6 V. Consequently, if the impurity concentration in the p-type well 51 of the field effect transistor 50 is set to suit the p-type base layer 11 of the main body 10, its withstand voltage will become 10 V or thereabout. Since it is necessary to apply a gate voltage 104 of about 15 V to the insulated-gate controlled semiconductor device to ensure its definite operation, the field effect transistor will not operate properly if its withstand voltage is lower than 15 V. Moreover, the setting of the impurity concentration in the p-type well 51 to a concentration different from that provided in the p-type base layer 11 is extremely disadvantageous in view of the manufacturing process.
The reason for the second problem lies in the fact that the field effect transistor, though it is of a horizontal type, is incorporated in the same chip affiliating the main body 10 and the overload detector 20. Consequently, there exits a vertical type thyristor of pnpn construction including the p-type substrate 111, the n-type buffer layer 112, the n-type epitaxial layer 113, the p-type well 51 of the field effect transistor, and the n-type drain layer 55. If, therefore, the parasitic thyristor is turned off while the insulated-gate controlled semiconductor device is held off, latchup will arise. Since few carriers in the epitaxial layer 113 of FIG. 7, holes in this example, are apt to flow into the well 51, the potential with respect to the drain layer 55 tends to rise. As the drain terminal 106 and the source terminal 107 are rendered at the same potential, the junction between the well 51 and the drain layer 55 is set in the forward bias state and thereby the parasitic thyristor is likely to be easily turned on.
The reason for the third problem lies in the fact that when the field effect transistor 50 is turned on and lowers the potential of the common insulated gate 105 during the overload protective operation, the current flowing through the overload detector 20 decreases, thus decelerating the voltage drop of the current detecting means 40. As a result, the gate voltage of the field effect transistor 50 decreases while its on-resistance increases and the potential of the insulated gate 105 rises, thus increasing the current in the main body. When the overload current flowing through the main body is large at the time of short-circuiting of the load, this process is repeated and oscillation is liable to occur.